III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si

Area of Science:

• Semiconductor Physics
• Materials Science
• Nanotechnology

Background:

• III-V semiconductors offer superior electronic properties for advanced logic circuits.
• Integrating III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on silicon (Si) substrates presents significant challenges.
• Existing methods struggle with cost-effective, large-scale integration for complementary metal-oxide-semiconductor (CMOS) applications.

Purpose of the Study:

• To demonstrate a novel approach for monolithic integration of III-V n- and p-type MOSFETs on Si.
• To overcome the limitations of current III-V/Si integration techniques.
• To enable high-performance, low-power logic circuits using III-V materials on silicon.

Main Methods:

• Simultaneous growth of InAs and InAs/GaSb vertical nanowires of equal length in a single step.
• Development of a dual-channel, single gate-stack design for both n- and p-type transistors.
• Fabrication of monolithic III-V MOSFETs on Si substrates.

Main Results:

• Achieved high on/off current ratios (I(on)/I(off)) for both n- and p-type III-V MOSFETs.
• Demonstrated successful monolithic integration of III-V MOSFETs on a Si substrate.
• Successfully fabricated fundamental CMOS logic gates, including inverters and NAND gates.

Conclusions:

• The novel nanowire growth and integration approach is viable for large-scale III-V MOSFET circuits on Si.
• This method paves the way for low-power, high-speed logic applications by combining III-V materials with silicon.
• The demonstrated CMOS logic gates highlight the potential for next-generation electronic devices.