Nanowire NMOS Logic Inverter Characterization.

Area of Science:

• Semiconductor device physics
• Nanotechnology
• Integrated circuit design

Background:

• Nanowire field-effect transistors (NWFETs) offer potential for scaled electronics.
• Logic inverters are fundamental building blocks in digital circuits.
• Optimizing NWFET inverter performance is crucial for next-generation integrated circuits.

Purpose of the Study:

• To optimize the transfer characteristics of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverters.
• To identify key parameters influencing noise margins and inflection voltage.
• To evaluate different circuit configurations for improved inverter performance.

Main Methods:

• Utilized a computer-based model to simulate static characteristics of NW-NMOS logic inverters.
• Investigated two distinct NW-NMOS inverter circuit configurations.
• Analyzed the impact of applied voltages and nanowire ratios on performance metrics.

Main Results:

• The first circuit configuration exhibited very low noise margins for low input-high output conditions.
• The second circuit configuration demonstrated excellent noise margins.
• Increasing gate-to-source voltage with a (2/1) nanowire ratio enhanced noise margins.
• Decreasing the applied DC load transistor voltage significantly improved noise margins.

Conclusions:

• Optimization of NW-NMOS logic inverters is achievable through careful selection of circuit configuration and operating voltages.
• Applied voltage and nanowire geometry are critical factors for achieving high noise margins.
• The findings provide a pathway for designing more robust and efficient NW-MOS based logic circuits.