Dimensional optimization of nanowire--complementary metal oxide--semiconductor inverter

Area of Science:

• Electrical Engineering
• Materials Science
• Nanotechnology

Background:

• Complementary metal-oxide-semiconductor (CMOS) inverters are fundamental logic gates.
• Nanowire transistors offer potential for scaled-down electronic devices.
• Optimization of nanowire dimensions is crucial for device performance.

Purpose of the Study:

• To perform dimensional optimization of nanowire-complementary metal-oxide-semiconductor (NW-CMOS) inverters.
• To investigate the impact of dimension ratios and digital voltage (Vdd) on inverter characteristics.
• To identify optimal dimensions for fabricating high-performance silicon nanowire transistors.

Main Methods:

• Utilized noise margins and inflection voltage of transfer characteristics as optimization limiting factors.
• Analyzed the relationship between Vdd and optimized dimension ratios (Dp/Dn, Lp/Ln).
• Investigated diameter and channel length optimization for NW-CMOS inverters.

Main Results:

• Optimization is dependent on both dimension ratios and Vdd.
• Increased Vdd leads to decreased optimized (Dp/Dn) and optimized Ln.
• Increased Vdd results in increased (Lp/Ln) and decreased (Kp/Kn).

Conclusions:

• Silicon nanowire transistors can be fabricated with suitable dimensions for optimal performance.
• Achieving optimal NW-CMOS inverter performance requires careful consideration of Vdd and dimensional ratios.
• The study provides a framework for dimensionally optimizing NW-CMOS inverters.