A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon...

Area of Science:

• Semiconductor device physics
• Nanotechnology
• Integrated circuit design

Background:

• Static Random-Access Memory (SRAM) is crucial for modern electronics.
• Silicon Nanowire Transistors (SiNWTs) offer potential for scaled-down memory devices.
• Optimizing SiNWT dimensions is key to improving SRAM performance and power efficiency.

Purpose of the Study:

• To explore dimensional optimization of SiNWT-based SRAM cells at different logic-level voltages.
• To investigate the impact of nanowire diameter and length on SRAM performance across various Vdd levels.
• To identify optimal Vdd ranges for nanoscale SiNWT-based SRAM cells.

Main Methods:

• Simulated dimensional optimization of SiNWT-based SRAM cells.
• Analyzed noise margins and inflection voltage of butterfly characteristics as optimization constraints.
• Evaluated performance metrics including dimensions, current, and power consumption at varying Vdd.

Main Results:

• Nanowire dimensions for SiNWT-based SRAM cells decrease with increasing Vdd (1 V to 3 V).
• Higher Vdd (1 V to 3 V) leads to increased current and power consumption.
• Optimal Vdd for reduced dimensions, inflection currents, and power consumption is between 2 V and 2.5 V.

Conclusions:

• SRAM performance is contingent upon both nanowire dimensions and Vdd.
• A Vdd of 2-2.5 V is recommended for SiNWT-based SRAM to achieve lower dimensions, inflection currents, and power consumption.
• This research provides critical insights for designing efficient nanoscale SRAM.