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Updated: Feb 20, 2026

05:57
Characterization of SiN Integrated Optical Phased Arrays on a Wafer-Scale Test Station
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Design and characterization of a p+/n-well SPAD array in 150nm CMOS process: erratum
Optics Express
|October 19, 2017
Abstract:
An erratum is presented to correct a reference mistake in Table 1 in Sect. 4 of [Opt. Express25, 12765 (2017)].
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