Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS...

Area of Science:

• * Electrical Engineering
• * Computer Engineering
• * Image Sensor Technology

Background:

• * Ultra-high-speed imaging requires advanced solutions for data handling and noise reduction.
• * Traditional imager architectures face limitations in frame depth and noise performance at high speeds.

Purpose of the Study:

• * To present a novel in-situ storage pixel topology for ultra-high-speed burst mode imagers.
• * To analyze system-level trade-offs concerning noise, power consumption, and scalability.
• * To develop a comprehensive noise model for optimizing pixel design.

Main Methods:

• * Proposed a pixel architecture with a 4T pinned photodiode, correlated double sampling (CDS) amplification, and in-situ memory.
• * Utilized an AC-coupled CDS stage with an NMOS transistor for amplification.
• * Developed a noise model to balance area and noise performance.
• * Fabricated a prototype imager in 130 nm CMOS technology with a 30 µm pixel pitch and a 108-cell memory bank.

Main Results:

• * Demonstrated low noise operation (8.4 e-) at high speeds up to 20 Mfps.
• * Achieved a high frame depth due to the in-situ memory bank.
• * Validated the pixel architecture's advantages in noise, power, and scalability.
• * Investigated two types of CDS amplification stages.

Conclusions:

• * The proposed in-situ storage topology is effective for ultra-high-speed burst mode imagers.
• * The pixel architecture offers a favorable trade-off between noise, power, and scaling.
• * The developed noise model aids in optimizing pixel design for specific applications.