Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

Area of Science:

• Semiconductor device physics
• Materials science
• Integrated circuit design

Background:

• Capacitorless one-transistor dynamic random-access memory (1T-DRAM) cells utilizing a polysilicon body offer cost-effective fabrication and enable 3D stacking for higher integration density.
• Grain boundaries (GBs) in polysilicon act as charge storage regions, crucial for the operation of these thin-body 1T-DRAM devices.

Purpose of the Study:

• To statistically analyze the impact of grain boundary (GB) number and location on the memory characteristics of polysilicon 1T-DRAM cells.
• To understand how GBs influence charge trapping and, consequently, memory performance metrics like sensing margin and retention time.

Main Methods:

• Technology Computer-Aided Design (TCAD) simulations were employed to model and analyze polysilicon 1T-DRAM cells.
• Statistical analysis was performed to correlate the number and spatial arrangement of GBs with memory performance.

Main Results:

• An increased number of GBs leads to a reduced sensing margin and shorter retention times due to enhanced trapped electron charge.
• Memory performance degrades significantly when GBs are located adjacent to the source or drain junctions, areas of strong electric fields, particularly affecting the "0" state current.

Conclusions:

• The number and location of grain boundaries within the polysilicon channel are critical design parameters for polysilicon 1T-DRAM.
• Optimizing GB characteristics is essential for achieving desired memory performance and reliability in polysilicon 1T-DRAM technology.