A 10.8 µW Neural Signal Recorder and Processor With Unsupervised Analog Classifier for Spike Sorting

Area of Science:

• Neuroscience
• Electrical Engineering
• Biomedical Engineering

Background:

• Implantable brain machine interfaces (BMIs) require efficient on-chip, real-time signal processing for neurological disorder treatments.
• Action potential (spike) detection and classification are critical for neural signal analysis in BMIs.

Purpose of the Study:

• To present the first spike sorting System-on-Chip (SoC) with integrated neural recording front-end and analog unsupervised classifier.
• To develop a low-power, hardware-optimized solution for real-time spike processing in implantable devices.

Main Methods:

• A novel hardware-optimized, K-means based algorithm for spike sorting was developed.
• The system utilizes a unique clockless and Analog-to-Digital Converter (ADC)-less analog architecture.
• The chip was fabricated in a 180-nm CMOS SOI process, measuring 1.4 mm².

Main Results:

• The analog front-end achieved a 3.3 μVrms noise floor and consumed 6.42 μW.
• The analog spike sorter consumed 4.35 μW and reached 93.2% classification accuracy on synthetic data.
• Over 93% agreement was observed with standard software using real neural signals, demonstrating robust performance.

Conclusions:

• The developed spike sorting SoC represents a significant advancement for implantable BMIs.
• The low-power, analog architecture offers efficient real-time processing capabilities for neurological applications.
• The chip demonstrates high accuracy and robustness, paving the way for improved neurological disorder treatments.