A Dynamically Reconfigurable ECG Analog Front-End With a 2.5× Data-Dependent Power Reduction.

Area of Science:

• Biomedical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• Electrocardiogram (ECG) analog front-ends (AFEs) are crucial for monitoring heart activity.
• Existing ECG AFEs often face challenges in balancing power consumption and signal fidelity.
• Reducing power consumption in wearable or implantable ECG devices is a key research area.

Purpose of the Study:

• To develop a reconfigurable ECG AFE with significantly reduced power consumption.
• To exploit the inherent characteristics of bio-signals for power optimization.
• To maintain or improve the accuracy of ECG feature extraction and anomaly detection.

Main Methods:

• Implementation of a reconfigurable ECG AFE in 65 nm CMOS technology.
• Utilizing an agile, on-the-fly dynamic noise-power trade-off strategy.
• Employing a least mean squares (LMS)-based adaptive predictor to guide power savings based on cardiac cycle regions.

Main Results:

• Achieved approximately 2.5x data-dependent power savings.
• Tunable input-referred noise ranging from 2.38 to 3.64 μVrms.
• Low power consumption between 307 and 769 nW from a 0.8 V supply.

Conclusions:

• The proposed predictor-based approach enables substantial power savings in ECG AFEs.
• The AFE demonstrates feasibility for power reduction without compromising diagnostic capabilities.
• This technology is suitable for low-power, high-performance wearable and implantable cardiac monitoring systems.