A Co-Designed Neuromorphic Chip With Compact (17.9K F²) and Weak Neuron Number-Dependent Neuron/Synapse Modules.

Area of Science:

• Neuromorphic Engineering
• Artificial Intelligence
• Computer Architecture

Background:

• Traditional neuromorphic cores face escalating hardware costs with increased neuron and synapse integration.
• Fully connected architectures lead to quadratic and linear cost increases for synapses, dendrites, and somas, respectively.

Purpose of the Study:

• To propose a co-designed neuromorphic core (SRCcore) that mitigates hardware cost growth.
• To leverage quantized spiking neural network (SNN) technology and compact chip design for improved efficiency.

Main Methods:

• Developed the SRCcore architecture with a neuron/synapse module whose cost is independent of neuron count.
• Implemented SRCcore in the BICS chip, utilizing a matched weight quantization strategy for SNNs.

Main Results:

• The SRCcore-based BICS chip demonstrates significantly reduced area (7.9%–38.6% of previous works) despite scaling neurons and synapses.
• Quantized SNNs achieved 0.05%–2.19% higher accuracy compared to prior methods.
• A cross-modeling application was successfully demonstrated on the chip.

Conclusions:

• SRCcore effectively reduces hardware area costs, enabling larger and more efficient neuromorphic systems.
• The co-design approach supports the application of quantized SNNs with enhanced accuracy.
• This work aims to accelerate the development of cortical-scale neuromorphic systems.