DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

Area of Science:

• Semiconductor Device Physics
• Advanced Transistor Technology
• Computational Electronics

Background:

• Conventional tunneling field-effect transistors (TFETs) face limitations in performance and scalability for emerging technology nodes.
• Complementary logic circuits require efficient and scalable transistor designs.

Purpose of the Study:

• To computationally investigate the electrical characteristics and performance of a novel 3D vertically stacked complementary tunneling field-effect transistor (CTFET).
• To assess the scalability and circuit-level performance of CTFETs as a potential alternative to conventional TFETs.

Main Methods:

• 3D device simulation of a CTFET with vertically stacked n-TFET and p-TFET using gate-all-around (GAA) nanosheet SiGe.
• Analysis of DC characteristics under process variability (traps, temperature).
• Evaluation of scalability based on critical dimensions and circuit performance (inverter analysis).

Main Results:

• CTFETs demonstrate high scalability with respect to critical dimensions.
• CTFET-inverter circuits exhibit significantly improved noise margins (NM) and voltage gains compared to conventional strained-Si GAA-TFETs.
• Performance analysis shows 12.5% and 21.5% improvements in low and high NMs, respectively.

Conclusions:

• CTFETs represent a highly scalable and promising technology for emerging nodes, offering superior circuit performance.
• The proposed 3D vertically stacked CTFET design is a viable alternative to conventional TFETs for next-generation integrated circuits.