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A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.

Xiping Jiang1,2,3, Xuerong Jia3,4, Song Wang3

  • 1Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China.

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Summary
This summary is machine-generated.

This study introduces a 3D integrated circuit (3DIC) platform using Wafer-on-Wafer bonding to overcome the memory wall. A novel Cross-Process Signal Integrity Analysis (CPSIA) method quantifies timing uncertainty from crosstalk in stacked DRAM and logic.

Keywords:
WoWcross-process analysis methodologysignal integritystacked DRAM

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Area of Science:

  • Electrical Engineering
  • Computer Engineering
  • Materials Science

Background:

  • The 'memory wall' limits performance by the gap between processor and memory speeds.
  • Multi-layer stacked Dynamic Random Access Memory (DRAM) offers a solution through high-density vertical interconnects.
  • Integrating diverse manufacturing processes in 3D Integrated Devices (3DICs) poses signal integrity challenges.

Purpose of the Study:

  • To develop a novel Cross-Process Signal Integrity Analysis (CPSIA) method for 3DIC platforms.
  • To analyze the impact of crosstalk on signal timing in vertically stacked memory and logic units.
  • To validate the CPSIA method's effectiveness in explaining physical testing results.

Main Methods:

  • Established a lumped circuit model based on 3DIC physical structure using transmission line models.
  • Developed the CPSIA method to integrate multiple manufacturing processes in a unified simulation environment.
  • Employed a dedicated buffer driving method alongside CPSIA for impact analysis.

Main Results:

  • Quantified timing uncertainty due to 3DIC crosstalk, ranging from 31 ps to 62 ps.
  • The CPSIA method successfully explained observed stable variations in maximum frequency in stacked memory arrays.
  • Demonstrated the practical effectiveness of the CPSIA method in analyzing complex 3DIC architectures.

Conclusions:

  • The developed CPSIA method provides accurate signal integrity analysis for multi-process 3DICs.
  • This approach effectively addresses challenges in designing and analyzing high-density stacked memory platforms.
  • The findings contribute to overcoming the memory wall by enabling robust 3DIC design.