A 1024-Channel 268 nW/pixel 36×36 μm2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer
MoonHyung Jang1, Maddy Hays2, Wei-Han Yu3
1Department of Electrical Engineering, Stanford University, CA 94305 USA.
IEEE Journal of Solid-State Circuits
|October 11, 2024
Summary
This study introduces a novel data-compressive integrated circuit for neural recording, significantly reducing data rates for brain-computer interfaces. It enables high-resolution signal capture with unprecedented energy efficiency.
Area of Science:
- Neuroscience
- Electrical Engineering
- Biomedical Engineering
Background:
- High-bandwidth neural recording is crucial for advanced brain-computer interfaces (BCIs).
- Existing systems face challenges with data deluge and high power consumption.
- Need for efficient, high-density neural recording solutions.
Purpose of the Study:
- To present a data-compressive neural recording integrated circuit (IC) for single-cell resolution BCIs.
- To demonstrate significant data rate reduction and high energy efficiency.
- To enable compact and low-power neural recording systems.
Main Methods:
- Implemented wired-OR lossy compression during analog-to-digital conversion.
- Utilized pulse position modulation-based active digital pixels with global single-slope ADC.
- Fabricated a 1024-channel IC in 28-nm CMOS technology with 36 μm pixel pitch.
Main Results:
- Achieved an average data rate reduction of 146× by discarding baseline samples.
- Demonstrated low input-referred noise (7.4 μVrms) and wide bandwidth (300 Hz–5 kHz).
- Attained minimal power consumption (268 nW) and the smallest area per channel (36 × 36 μm²).
Conclusions:
- The developed IC offers a breakthrough in data compression for neural recording.
- It represents the most energy-efficient and compact neural recording IC to date.
- This technology paves the way for next-generation, high-performance BCIs.
