Self-cleaning van der Waals lamination for two-dimensional electronics

Van der Waals (vdW) lamination, a low-energy physical stacking technique, holds great promise for two-dimensional (2D) electronics and future three-dimensional (3D) integration. However, achieving ultra-clean interfaces-free from interlayer molecular contaminants-remains a significant challenge. Here, we introduce an elastic bevel stamp-assisted thermal lamination (EBTL) technology, operated at 150 °C, which actively self-expels interlayer molecular impurities (e.g., water, oxygen), eliminating bubbles, wrinkles, and defects, yielding pristine vdW interfaces. Through nanomechanical analysis, we optimize key parameters of bevel stamp, such as angle and size, to ensure clean and damage-free lamination of 2D monolayer at large scales. This method enables reliable preparation of ultra-clean 2D stacked structures with an average interface yield >95%. Devices fabricated with it exhibit improved performance compared to conventional methods, as evidenced by hysteresis-free hBN top-gate transistors (∼10 mV) and ultrafast hetero-diodes (470 ns). The lamination of wafer-scale monolayers, twisted bilayers, and complex superlattices can be readily achieved with clean interfaces. It is also applicable to clean lamination of various building blocks, such as 2D channels, 3D metals, and dielectrics. We therefore demonstrate a fully vdW-laminated 2D transistor array (2400 transistors on a 0.25 cm² area), where all components are stacked along the z-direction, achieving low device-to-device variability. Our work provides a promising approach for clean vdW integration and high-performance vdW electronics.