A low-power 32-channel digitally programmable neural recording integrated circuit

Area of Science:

• Neuroscience
• Electrical Engineering
• Biomedical Engineering

Background:

• High-density neural recording is crucial for understanding brain function.
• Existing integrated circuits often face limitations in power consumption and channel count.
• Developing energy-efficient neural recording systems is essential for advanced brain-computer interfaces.

Purpose of the Study:

• To design and characterize an ultra-low-power 32-channel neural-recording integrated circuit.
• To achieve high energy efficiency and area efficiency for scalable neural recording applications.
• To validate the chip's performance in in vivo experiments.

Main Methods:

• Utilized a 0.18 μm CMOS technology for chip fabrication.
• Incorporated an adaptive-biasing scheme to minimize amplifier power consumption.
• Integrated neural amplifiers, analog multiplexers, and 8-bit ADCs per module.
• Employed AC coupling for wide dynamic range and DC operation.

Main Results:

• Achieved an ultra-low power consumption of 10.1 μW per channel in vivo.
• Demonstrated programmable gain (49-66 dB) for spike and LFP recording.
• The ADC achieved 7.65 effective bits (ENOB) with 77 fJ/State efficiency.
• The chip showed successful in vivo wireless recording from a behaving primate.

Conclusions:

• The designed integrated circuit offers a highly power-efficient and area-efficient solution for neural recording.
• The adaptive-biasing scheme significantly reduces power consumption based on noise levels.
• The chip's performance enables scaling to high channel-count systems for advanced neuroscience research.
• This technology facilitates more sophisticated and long-term neural monitoring applications.