Negative-Capacitance Fin Field-Effect Transistor Beyond the 7-nm Node

In this paper, we investigate the negative-capacitance fin field-effect (NC-FinFET) and extend the design beyond the 7-nm technology node. A 7-nm-node NC-FinFET is presented using the Landau-Khalatnikov equation and the physical equations of a 3D technology computer-aided design simulation. We propose a new NC-FinFET with double ferroelectric hafnium zircon dioxide layers. This device exhibits noticeable voltage gains in the sub-threshold region, can decrease subthreshold swing (SS) effectively, has a wide-ranged uniform SS lower than 60 mV/dec, and can downscale the threshold voltage without increasing the off current. The static noise margin of the static random access memory using the new NC-FinFET is simulated and shows good performance with improved SS and threshold voltage.