Self-controlled multilevel writing architecture for fast training in neuromorphic RRAM applications

Area of Science:

• Materials Science and Engineering
• Electrical Engineering
• Computer Science

Background:

• Memristor crossbar arrays offer natural acceleration for neural network applications through parallel multiply-add operations.
• The abrupt SET operation in Resistive Random-Access Memory (RRAM) devices complicates on-chip training, often requiring iterative stages or complex circuitry.
• Achieving multilevel capabilities in memristors is crucial for advanced neural network implementations.

Purpose of the Study:

• To present a self-controlled architecture for programming multilevel memristor devices.
• To enable programming with a short and fixed operation duration, overcoming limitations of abrupt SET operations.
• To facilitate efficient on-chip training for neural network applications.

Main Methods:

• Development of an ad hoc scheme to self-control the abrupt SET operation by modulating the writing stimulus.
• Utilization of the voltage divider concept with a series variable resistive load to manage cell programming.
• Validation through thorough simulations using fast physical RRAM cells and commercial 40 nm CMOS technology, incorporating device variability.

Main Results:

• The proposed architecture successfully programs multilevel memristor devices with a self-controlled, abrupt SET operation.
• Progressive and nearly linear resistive levels were achieved in both [Formula: see text] and [Formula: see text] crossbar structures.
• The method demonstrated effectiveness even with inherent device variability and fast switching characteristics.

Conclusions:

• The developed self-controlled architecture provides an efficient solution for programming multilevel memristor devices.
• This approach simplifies on-chip training for neural networks by enabling precise control over memristor states.
• The findings pave the way for more robust and high-performance neuromorphic computing systems.