Variability-Aware Simulation Strategy for Gate-All-Around Vertical Field Effect Transistor.

Area of Science:

• Semiconductor device physics
• Advanced transistor technology

Background:

• Gate-all-around (GAA) vertical field-effect transistors (VFETs) offer enhanced gate area efficiency for advanced semiconductor nodes.
• Variability sources like work function variation (WFV) and global variability (GV) critically impact device performance at the 5nm node and below.

Purpose of the Study:

• To investigate the impact of work function variation (WFV) and global variability (GV) on 5nm node GAA silicon VFETs.
• To analyze the interplay between WFV, GV, and gate controllability in VFETs.
• To provide guidelines for managing integrated variability in VFET device structures and 6-T SRAM bit cells.

Main Methods:

• Technology computer-aided design (TCAD) simulations were employed to model VFET behavior.
• SPICE simulations utilizing the BSIM-CMG model were performed to assess device performance.
• Analysis encompassed various VFET device structures within single devices and 6-T SRAM bit cells.

Main Results:

• Increased gate area in VFETs reduces the impact of WFV but can worsen GV due to weakened gate controllability.
• Integrated analysis of WFV and GV is crucial for understanding variability issues in VFETs.
• The study identifies specific challenges and opportunities for variability mitigation in advanced VFET designs.

Conclusions:

• Accurate guidelines are proposed for addressing integrated variability challenges in 5nm GAA silicon VFETs.
• Understanding the combined effects of WFV and GV is essential for reliable VFET and SRAM bit cell design.
• The research contributes to the development of robust nanoscale semiconductor devices.