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A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers
Aria Samiei1, Hossein Hashemi1
1Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA 90089 USA.
Summary
This study introduces a novel neural interface chip for simultaneous brain recording and stimulation. Its integrated artifact cancelers effectively reduce interference, improving signal quality for neural data acquisition.
Area of Science:
- Biomedical Engineering
- Neurotechnology
- Integrated Circuit Design
Background:
- Neural interfaces are crucial for understanding brain function and treating neurological disorders.
- Simultaneous neural recording and stimulation present challenges due to stimulus artifacts.
- Existing artifact cancellation methods often require external processing or are less efficient.
Purpose of the Study:
- To develop a compact, low-power neural interface system-on-chip (SoC) with integrated artifact cancellation.
- To enable high-fidelity simultaneous neural recording and stimulation.
- To reduce the impact of stimulation artifacts on neural signal acquisition.
Main Methods:
- Designed a 180-nm CMOS bidirectional neural interface SoC.
- Implemented on-chip stimulus artifact cancelers using a least-mean-square engine and adaptive infinite-impulse-response (IIR) filters.
- Utilized a front-end cancellation scheme to replicate and subtract artifact waveforms.
Main Results:
- Demonstrated artifact mitigation up to 700 mVpp.
- Reduced front-end amplifier saturation recovery time for a 2.5 Vpp artifact.
- Achieved low power consumption (2.5 μW/channel) with high gain (50 dB) and bandwidth (9.0 kHz).
- Reported low integrated input-referred noise (6.2 μVrms).
Conclusions:
- The developed neural interface SoC effectively cancels stimulation artifacts.
- On-chip adaptive IIR filters enable simultaneous recording and stimulation with minimal artifact impact.
- This technology advances the development of sophisticated neural prosthetics and brain-computer interfaces.

