An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition.

Area of Science:

• Neuroscience
• Electrical Engineering
• Biomedical Engineering

Background:

• High-channel-count neural recording interfaces are crucial for advanced brain-computer interfaces.
• Existing architectures often face trade-offs between power efficiency, area, and signal fidelity.
• There is a growing need for integrated circuits that can simultaneously capture diverse neural signals like LFPs and APs.

Purpose of the Study:

• To develop a miniature 128-channel neural recording integrated circuit (NRIC) for simultaneous acquisition of local field potentials (LFPs) and action potentials (APs).
• To achieve a superior compromise between area, power consumption, noise, input range, and electrode DC offset cancellation.
• To leverage a digitally-intensive architecture in a highly-scaled technology node for improved performance.

Main Methods:

• Proposed an AC-coupled 1st-order digitally-intensive architecture.
• Fabricated a prototype NRIC with 128 channels using 22-nm FDSOI CMOS technology.
• Included an area-efficient bulk-regulated voltage reference, biasing circuits, and digital control.

Main Results:

• Achieved a total area per channel of 0.005 mm² and power per channel of 12.57 µW.
• Reported input-referred noise of 7.7 ± 0.4 µVrms in the AP band and 11.9 ± 1.1 µVrms in the LFP band.
• Demonstrated excellent channel-to-channel uniformity and successful in vivo validation for full-band neural signal recording.

Conclusions:

• The developed NRIC offers a highly area- and power-efficient solution for high-channel-count neural recording.
• The proposed architecture successfully balances key electrical performance metrics, meeting the demands for advanced neural interfaces.
• The NRIC's in vivo performance confirms its viability for real-world neural signal acquisition applications.