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Metal-free high-contrast wafer-level step height standards with large height-range based on all-dielectric
Jinming Gou1,2,3,4,5,6, Yuying Xie1,2,3,4,5,6, Xiao Deng1,2,3,4,5,6
1National Metrology and Testing Center for Integrated Circuit Measurement and Inspection Equipment Industry (Shanghai), Tongji University, Shanghai 200092, People's Republic of China.
Nanotechnology
|June 23, 2025
Summary
New silicon-on-insulator (SOI) dielectric multilayers offer high optical contrast wafer-level step height standards. This approach enhances integrated circuit inspection accuracy and avoids metal contamination issues common with conventional methods.
Area of Science:
- Materials Science
- Nanotechnology
- Semiconductor Manufacturing
Background:
- Accurate wafer-level step height standards are essential for automated inspection in integrated circuit (IC) manufacturing.
- Conventional standards using single-layer films (Si-SiO2) often require metal coatings, risking particle contamination.
- Low optical contrast in standard step height measurements hinders precise automatic image recognition.
Purpose of the Study:
- To develop a novel wafer-level step height standard with high optical contrast.
- To mitigate metal particle contamination issues present in traditional step height standards.
- To improve the accuracy and efficiency of automatic image recognition in IC inspection.
Main Methods:
- Design of silicon-on-insulator (SOI) dielectric multilayers (Si-SiO2-Si) to maximize reflectance ratio for high contrast.
- Fabrication of 20 nm, 100 nm, and 500 nm step height standards on 8-inch wafers.
- Utilizing film deposition, electron-beam lithography, and dry etching techniques.
Main Results:
- Achieved optical contrast two orders of magnitude higher than conventional single-layer standards.
- Maintained high precision in step height measurement across designed standards.
- Demonstrated consistent high contrast across varying step heights.
Conclusions:
- The proposed SOI multilayer step height standards provide superior optical contrast.
- This technology enhances image recognition efficiency in IC inspection.
- It effectively reduces the risk of metal contamination in semiconductor production lines.
