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Updated: Feb 14, 2026

Preparation of Silicon Nanowire Field-effect Transistor for Chemical and Biosensing Applications
Published on: April 21, 2016
Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
1Faculty of Engineering Technology, University Malaysia Pahang (UMP), Lebuhraya Tun Razak, 26300, Pahang, Malaysia.
Abstract:
This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20-1000 KΩ with Vdd = 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100-200 KΩ.
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