A Power-Efficient Bridge Readout Circuit for Implantable, Wearable, and IoT Applications

Area of Science:

• Integrated Circuits
• Sensor Interfaces
• Biomedical Engineering

Background:

• Resistive bridge sensors are crucial for implantable, wearable, and IoT applications, including intracranial pressure (ICP) and blood pressure (BP) monitoring.
• Traditional interfaces often suffer from high static power consumption and susceptibility to power supply noise.
• Existing fully-differential topologies can be complex and area-intensive.

Purpose of the Study:

• To propose a novel power-efficient bridge-to-digital sensing interface with enhanced immunity to power supply noise.
• To reduce the static power consumption of resistive bridge sensors through duty-cycling.
• To present a simplified interface topology compared to traditional fully-differential designs.

Main Methods:

• Utilized duty-cycling to minimize static power consumption of resistive bridge sensors.
• Employed a revised pseudo-pseudo differential (PPD) topology combined with the ping-pong technique.
• Fabricated a proof-of-concept prototype in 0.35-μm CMOS technology.

Main Results:

• Achieved 9.13 effective number of bits (ENOB) at a 3.72 kHz sampling rate.
• Demonstrated over 50 dB improvement in power supply rejection ratio (PSRR) using the ping-pong technique.
• Reduced power consumption of a 5-kΩ Wheatstone bridge by 99.6% to 2.53 μw at 1.8 V supply.

Conclusions:

• The proposed interface offers significant power savings and improved noise immunity for resistive bridge sensors.
• The simplified PPD topology with ping-pong technique reduces complexity and area.
• Demonstrated practical functionality with an embedded resistive bridge pressure sensor in an experimental setup.