An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array

Area of Science:

• Materials Science
• Electrical Engineering
• Solid-State Electronics

Background:

• Resistive random access memory (RRAM) is a promising embedded non-volatile storage technology for advanced CMOS modules.
• The practical application of RRAM is significantly limited by its endurance and cyclability.

Purpose of the Study:

• To investigate the relationship between noise characteristics, filament configurations, and reset failure in RRAM during cycling.
• To develop methods for improving RRAM cyclability and overall array endurance.

Main Methods:

• Detailed analysis of noise types and filament configurations in RRAM devices.
• Cycling tests to evaluate RRAM performance and identify failure mechanisms.
• Development and testing of a recovery treatment for RRAM cyclability.
• Proposal of an early detection circuit for vulnerable RRAM cells.

Main Results:

• Established clear links between specific noise types, filament structures, and the occurrence of reset failure.
• Demonstrated a recovery treatment that effectively restores RRAM cyclability.
• Proposed an early detection circuit capable of identifying vulnerable cells within an RRAM array.
• Achieved RRAM array lifetimes exceeding 10,000 cycles without fail bits.

Conclusions:

• Understanding the interplay of noise and filament properties is key to mitigating RRAM reset failures.
• A novel recovery treatment and an early detection circuit significantly enhance RRAM endurance and reliability.
• RRAM technology shows potential for extended operational lifetimes, crucial for next-generation embedded storage solutions.